Manufacture of an integrated circuit isolation structure

US6319796A · kind A · utility

Assignee

• VLSI Technology, Inc. · US

Inventors

• Olivier Laparra · San Jose, US
• Ramiro Solis · Bandera, US
• Hunter B. Brugge · San Antonio, US
• Michela S. Love · San Antonio, US
• Bijan Moslehi · Stanford, US
• Milind Weling · San Jose, US

Key dates

• Filing date: Aug 18, 1999
• Grant date: Nov 20, 2001
• Expiry date: Aug 18, 2019

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S148/05
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Disclosed are techniques to provide an integrated circuit, including the provision of improved integrated circuit isolation structures. The techniques include forming a number of trenches in an integrated circuit substrate to define a number of substrate regions that are to be electrically isolated from one another. A dielectric material is deposited in the trenches by exposure to a high density plasma having a first deposition-to-etch ratio. The high density plasma is adjusted to a second deposition-to-etch ratio greater than the first ratio to accumulate the dielectric material on the substrate after at least partially filling the trenches. A portion of the dielectric material is removed to planarize the workpiece. A number of components, such as insulated gate field effect transistors, may be subsequently formed in the substrate regions between the trenches.