Process for passivating top interface of damascene-type Cu interconnect lines
US6319819A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 18, 2000 |
| Grant date | Nov 20, 2001 |
| Priority date | — |
| Expiry date | Jan 18, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76886
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The reliability, electromigration resistance, adhesion, and electrical contact resistance of planarized metallization patterns, e.g., of copper, in-laid in the exposed upper surface of a layer of dielectric material, are enhanced by a process comprising blanket-depositing on the planarized, exposed upper surfaces of the metallization features and the dielectric layer at least one thin layer comprising at least one passivant element for the metal of the features, reacting the at least one passivant element to chemically reduce any deleterious oxide layer present at the upper surfaces of the metallization features, and diffusing the at least one passivant element for a distance below the upper surface to form passivated top interfaces. The passivated top interfaces advantageously exhibit reduced electromigration and improved adhesion to overlying metallization with lower ohmic contact resistance. Planarization, as by CMP, may be performed subsequent to reaction/diffusion to remove any elevated, reacted and/or unreacted portions of the at least one thin layer. The invention finds particular utility in "back-end" metallization processing of high-density integrated circuit semiconductor…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.