Bottom-gated thin film transistors comprising germanium in a channel region
US6320202A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 12, 1999 |
| Grant date | Nov 20, 2001 |
| Priority date | — |
| Expiry date | Oct 12, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6748
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A thin film transistor includes, a) a thin film source region; b) a thin film drain region; c) a polycrystalline thin film channel region intermediate the thin film source region and the thin film drain region; d) a transistor gate and gate dielectric operatively positioned adjacent the thin film channel region; and e) the thin film channel region comprising at least an inner layer, an outer layer and a middle layer sandwiched between the inner layer and the outer layer, the inner layer and the outer layer comprising polycrystalline silicon and having respective energy bandgaps, the middle sandwich layer comprising a polycrystalline material and having a lower energy bandgap than either of the inner and outer layers. Alternately, the channel region is homogeneous, comprising germanium or an alloy of polycrystalline silicon and germanium. A method of increasing the size of individual crystal grains in a polycrystalline silicon alloy includes, a) providing germanium atoms within a layer of polycrystalline silicon to form a polycrystalline silicon-germanium alloy; and b) heating the polycrystalline silicon-germanium alloy to an effective temperature for an effective period of time to …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.