Gate structure for integrated circuit fabrication
US6320238A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 25, 1999 |
| Grant date | Nov 20, 2001 |
| Priority date | — |
| Expiry date | Jun 25, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a gate stack structure having a dielectric material layer disposed on a substrate with a gate electrode disposed thereon. In an exemplary embodiment, the dielectric material layer has an equivalent electrical thickness of 2.2 nm or less and includes at least one layer other than silicon dioxide. Furthermore, the dielectric material layer of the present invention enables device scaling and provides (1) decreased leakage current and improved tunneling voltage compared to a conventional gate dielectric; and (2) avoids the perils of ultra-thin silicon dioxide when used exclusively as the gate dielectric.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.