Flexible and programmable BIST engine for on-chip memory array testing and characterization
US6321320A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 1998 |
| Grant date | Nov 20, 2001 |
| Priority date | — |
| Expiry date | Oct 30, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A highly flexible and complex BIST engine provides at-speed access, testing, characterization, and monitoring of on-chip memory arrays, independent of other chip circuitry such as a CPU core. Each BIST engine has a main control block, at least one address generation block having an address local control block and one or more address-data generation blocks, and at least one data generation block having a data local control block and one or more data generation blocks. Each of the local address and data control blocks are programmed independently to define operations that will be performed by the individual address and data generation blocks, respectively. The main control block in turn controls operation of the local address and data control blocks to effect desired testing, accessing, and monitoring of the on-chip memory arrays.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.