Low-K dual damascene integration process
US6323123A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 6, 2000 |
| Grant date | Nov 27, 2001 |
| Priority date | — |
| Expiry date | Sep 6, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76808
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A barrier layer is formed over the substrate by deposition, and a first dielectric is formed over the diffusion barrier layer by deposition. A etching stop layer and a second dielectric are formed in turn over the first dielectric by deposition. Next, a hard mask is formed on the second dielectric. Then, a photoresist layer is formed over the hard mask, and defining the photoresist layer. And then dry etching is carried out by means of the photoresist layer as the mask to form a via hole. A gap-filling material is filled on the second dielectric and into the via hole by conventional partial-cured (or un-cured) spin-on glass method. A anti-reflection layer is formed over the second dielectric by deposition. Another photoresist layer is formed on the anti-reflection coating and defined the photoresist layer, and to expose the partial surface of the via hole and the anti-reflection coating. Dry etching is proceed by means of the photoresist layer as a mask, and etching stop layer is as a etching terminal point to remove exposed partial surface of the bottom anti-reflection coating so as to form a trench. Then, the gap-filling material is removed by wet etching. Then a barrier layer is…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.