Flash memory device and fabrication method having a high coupling ratio
US6323516A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 3, 1999 |
| Grant date | Nov 27, 2001 |
| Priority date | — |
| Expiry date | Sep 3, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6891
Abstract
Embodiments of the invention comprise a new device and technique to realize an improved coupling ratio integrated circuit device. This improvement is achieved by increasing an overlap portion between the first and second polysilicon layers, so as to increase the effective coupling ratio between the layers. In the embodiments of the present invention, a relatively tall or large portion of oxide is formed over at least a portion of each of a plurality of shallow trench isolation regions. This oxide is then utilized to provide a larger first polysilicon layer surface area, but without substantially increasing the tunnel oxide layer surface area. Then, a dielectric interlayer is formed upon the surface of the first polysilicon layer, and next, a second polysilicon layer is formed upon the dielectric interlayer. This increased overlap portion thus allows for an increased coupling ratio. Further, the coupling ratio may be tailored by adjusting either or both of the first and second polysilicon layer surface areas without requiring a substantial change in the tunnel oxide layer surface area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.