Ultrathin, nitrogen-containing MOSFET sidewall spacers using low-temperature semiconductor fabrication process
US6323519A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 23, 1998 |
| Grant date | Nov 27, 2001 |
| Priority date | — |
| Expiry date | Oct 23, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/671
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A transistor and a method for making a transistor are described. A gate conductor is patterned over a gate dielectric upon a semiconductor substrate. Dopant impurity distributions self-aligned to the gate conductor may be introduced. A conformal oxide having thickness between about 100 angstroms and 500 angstroms is deposited over the gate conductor and substrate. The oxide is exposed to a nitrogen-bearing plasma for conversion to nitrided oxide. Anisotropic etching may then be used to form ultrathin, nitrided oxide spacers. Introduction of a second dopant impurity distribution may be performed to create source-drain regions having narrow LDD regions, and resulting decreased series resistance and increased saturated drain current. Thicker spacers or spacers combining oxide and nitrided oxide portions may firther be formed by repeated deposition of thin conformal oxides. The presence of nitrogen in nitrided oxide portions of the spacers is believed to help prevent dopant outdiffusion from adjacent silicon, prevent silicide bridging across spacers, and increase resistance of the spacers to oxide etchants.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.