Single poly non-volatile memory structure and its fabricating method
US6324097A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 1999 |
| Grant date | Nov 27, 2001 |
| Priority date | — |
| Expiry date | Aug 26, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/10
Abstract
The present invention discloses a single poly non-volatile memory structure including a semiconductor substrate with two active areas divided by isolation regions. A control gate doped with N-type impurities is embedded in the first active area, and a first floating gate is formed thereon. A second floating gate is formed on the substrate of the second active area, and two doped regions are implanted at opposite sides of the second active areas in the substrate. A floating gate line is employed to connect the first and second floating gate for making sure that the two floating gates are in the same potential. When the control gate is biased to a voltage level, the voltage level would be coupled to the first floating gate so as to keep the second floating gate in the same potential with the first floating gate. While one of the doped regions is biased to a voltage level, electrons would eject from the other doped region and trapped in the floating gates, thereby preserving information in this memory structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.