Gate prespacers for high density, high performance DRAMs

US6326260A · kind A · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Ramachandra Divakaruni · Ossining, US
• James W. Adkisson · Jericho, US
• Mary E. Weybright · Pleasant Valley, US
• Scott D. Halle · Slingerlands, US
• Jeffrey P. Gambino · Gresham, US
• Heon Lee · Sunnyvale, US

Key dates

• Filing date: Jun 22, 2000
• Grant date: Dec 4, 2001
• Expiry date: Jun 22, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/05

Abstract

A memory device structure is provided in which the array oxide layer has a thickness that is greater than the thickness of the support oxide layer. Specifically, the structure comprises a semiconductor substrate having a gate oxide layer formed thereon, said substrate including array regions and support regions, said array regions include at least one patterned gate conductor, said patterned gate conductor having a polysilicon layer formed on said gate oxide layer, a conductor material layer formed on said polysilicon layer, and a nitride cap layer formed on said conductor material layer, said nitride cap layer and said conductor material layer having spacers formed on sidewalls thereof and said polysilicon layer having an array oxide layer formed on sidewalls thereof, said spacers being substantially flush with the oxide sidewalls, said support regions include at least one patterned gate conductor, said patterned gate conductor having a polysilicon layer formed on said gate oxide layer, a conductor material layer formed on said polysilicon layer, and a nitride cap layer on said conductor material layer, said polysilicon layer having a support oxide layer formed on sidewalls thereo…