Method of fabricating a deep trench capacitor
US6326261A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 5, 2001 |
| Grant date | Dec 4, 2001 |
| Priority date | — |
| Expiry date | Jan 5, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/0385
Abstract
A method of fabricating a deep trench capacitor is achieved. A deep trench is formed in a silicon substrate followed by the formation of a buried plate in the silicon substrate beneath the deep trench. A silicon nitride layer is formed on the surface of the deep trench above the buried plate. An oxidation process is performed to simultaneously form a first oxide film on the silicon nitride layer and a second oxide film on the silicon substrate within the deep trench. A doped polysilicon layer is formed in the deep trench with its surface lowered down to the surface of the substrate. Finally, a portion of the second oxide film is removed to expose the substrate in the upper region of the deep trench followed by the filling in of an undoped polysilicon layer into the deep trench to finish the fabrication process of the DRAM deep trench capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.