Method for manufacturing a semiconductor device
US6326299A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 28, 1999 |
| Grant date | Dec 4, 2001 |
| Priority date | — |
| Expiry date | Jul 28, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/7684
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In order to suppress an increase of depressions, etc. to occur on a copper based alloy layer during polishing when a copper based alloy inlaid wiring is formed with the damascene method in grooves formed in an insulating film, the polishing rate for the lower metallic layer is set not less than five times faster than the etching rate for the same and the polishing rate for the insulating film is set lower than the polishing rate for the lower metallic layer when the upper metallic layer 13 to become a wiring and the lower metallic layer 12 to become a barrier are polished respectively. Thus, the object damascene wiring can be formed with less erosion on each of insulating layers and dishing on each of metallic layers respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.