Low profile semiconductor package and process for making the same
US6326700A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 15, 2000 |
| Grant date | Dec 4, 2001 |
| Priority date | — |
| Expiry date | Aug 15, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A low-profile semiconductor device is disclosed which includes a substrate having a base layer formed with at least a hole and a plurality of conductive traces arranged on the base layer. A semiconductor die is attached to the base layer of the substrate opposite to the conductive traces and electrically connected to the conductive traces by a plurality of first conductive elements passing through the hole of the base layer. A plurality of second conductive elements are arrayedly connected to the terminal of each of the conductive traces for providing externally electrical connection to the semiconductor die. The semiconductor die is encapsulated by a first encapsulant formed on the surface of the substrate on which the semiconductor die is mounted. A second encapsulant is formed on the surface of the substrate on which the conductive traces are arranged to completely encapsulate the conductive traces, first conductive elements and the hole. Meanwhile, the second encapsulant is formed to encapsulate the second conductive elements in such a manner that the bottom ends of the second conductive elements are exposed to and flush with the bottom surface of the second encapsulant.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.