Method of forming a lower storage node of a capacitor for dynamic random access memory
US6329291A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 28, 2000 |
| Grant date | Dec 11, 2001 |
| Priority date | — |
| Expiry date | Jan 28, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/0335
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is disclosed for forming the lower storage node and contact for capacitors on a semiconductor wafer. The method includes an etch back process to remove a portion of the silicon oxide layer around the mouth of the contact hole to produce a rounded shoulder where the walls of the contact hole meet the face of the silicon oxide layer. When a contact plug is formed during a subsequent deposition process, the rounded shoulder results in local enlargement of the contact plug as well as filleting of reentrant corners. The contact plug therefore sustains substantially reduced mechanical stress during subsequent wafer cleaning processes. This stress reduction results in a reduced rate of lower node collapse and increased production yield of finished product.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.