High speed I/O calibration using an input path and simplified logic
US6330194A · kind A · utility
46Cited by
2References
66Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2000 |
| Grant date | Dec 11, 2001 |
| Priority date | — |
| Expiry date | Jun 26, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a calibration circuit for data paths DQ0 . . . DQN of a memory device by using a masking data path and an output buffer circuit provided therein in the calibration process. Calibration of the masking data path output buffer circuit is achieved and the calibrate results are transferred to each of the buffer amplifiers in the data paths DQ0 . . . DQN.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.