System for linearizing a programmable delay circuit
US6330197A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2000 |
| Grant date | Dec 11, 2001 |
| Priority date | — |
| Expiry date | Jul 31, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0818
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A random access memory (RAM) having N addressable storage locations is addressed by input data specifying a signal delay, and the RAM reads out control data controlling the delay of a delay circuit. A linearization system automatically adjusts the value of the control data stored at each of the RAM's N addresses so that the delay provided by the delay circuit is a linear function of the value of the input data. The linearization system provides two periodic reference signals ("beat" and "clock") wherein the period P.sub.B of the beat signal and the period P.sub.C of the clock signal are related by the expression P.sub.B =P.sub.C (N+1)/N. The linearization system iteratively adjusts the control data stored at each RAM address so that when the RAM continuously reads out the control data stored at the Kth RAM address, the Kth edge of the beat signal and every Nth edge thereafter substantially coincides with an edge of the delay circuit output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.