Method and system for embedded chip erase verification
US6331951A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 21, 2000 |
| Grant date | Dec 18, 2001 |
| Priority date | — |
| Expiry date | Nov 21, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3445
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system are disclosed for verifying memory cell erasure, which may be employed in association with a dual bit memory cell architecture. The method includes selectively verifying proper erasure of one of a first bit of the cell and a second bit of the cell, determining that the dual bit memory cell is properly erased if the first and second bits of the cell are properly erased, and selectively erasing at least one of the first and second bits of the cell if one of the first and second bits is not properly erased. The method may also comprise selectively re-verifying proper erasure of one of the first and second bits after selectively erasing at least one of the first and second bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.