Darlene Hamilton
69Patents
22h-index
96Co-inventors
87Inventor score
Filing activity: Jan 12, 1995 → Aug 8, 2012
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7440333B2 | Method of determining voltage compensation for flash memory devices | Physics | 226 | Active |
| US7038950B1 | Multi bit program algorithm | Physics | 121 | Expired |
| US7130210B2 | Multi-level ONO flash program algorithm for threshold width control | Physics | 98 | Expired |
| US6631086B1 | On-chip repair of defective address of core flash memory cells | Physics | 94 | Expired |
| US7010736B1 | Address sequencer within BIST (Built-in-Self-Test) system | Physics | 86 | Expired |
| US6567303B1 | Charge injection | Physics | 76 | Expired |
| US6442074B1 | Tailored erase method using higher program VT and higher negative gate erase | Physics | 73 | Expired |
| US6590811B1 | Higher program VT and faster programming rates based on improved erase methods | Physics | 68 | Expired |
| US6307784A | Negative gate erase | Electricity | 62 | Expired |
| US6512701B1 | Erase method for dual bit virtual ground flash | Physics | 52 | Expired |
| US6456533B1 | Higher program VT and faster programming rates based on improved erase methods | Physics | 50 | Expired |
| US8000127B2 | Method for resetting a resistive change memory element | Physics | 50 | Active |
| US6493266B1 | Soft program and soft program verify of the core cells in flash memory array | Physics | 48 | Expired |
| US6331951A | Method and system for embedded chip erase verification | Physics | 39 | Expired |
| US6735114B1 | Method of improving dynamic reference tracking for flash memory unit | Physics | 37 | Expired |
| US6344994B1 | Data retention characteristics as a result of high temperature bake | Physics | 34 | Expired |
| US6967873B2 | Memory device and method using positive gate stress to recover overerased cell | Physics | 34 | Expired |
| US6791880B1 | Non-volatile memory read circuit with end of life simulation | Physics | 26 | Expired |
| US6707078B1 | Dummy wordline for erase and bitline leakage | Physics | 24 | Expired |
| US6799256B2 | System and method for multi-bit flash reads using dual dynamic references | Physics | 24 | Expired |
| US7113431B1 | Quad bit using hot-hole erase for CBD control | Physics | 24 | Expired |
| US8391070B2 | Moving program verify level for programming of memory | Physics | 22 | Active |
| US8938655B2 | Extending flash memory data retension via rewrite refresh | Physics | 21 | Active |
| US6822909B1 | Method of controlling program threshold voltage distribution of a dual cell memory device | Physics | 16 | Expired |
| US6778442B1 | Method of dual cell memory device operation for improved end-of-life read margin | Physics | 16 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.