Processes for reduced topography capacitors
US6333239A · kind A · utility
1Cited by
15References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 21, 2000 |
| Grant date | Dec 25, 2001 |
| Priority date | — |
| Expiry date | Mar 21, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/716
Abstract
A planarized interleaved capacitor for use with a substrate. The capacitor has a plurality of planarized metal layers formed above the substrate, at least one dielectric layer disposed between the plurality of planarized metal layers, and at least one insulator layer disposed over one of the plurality of metal layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.