Integrated circuit vertical trench device and method of forming thereof

US6335247B1 · kind B1 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Helmut Tews · Poughkeepsie, US
• Alexander Michaelis · Wappingers Falls, US
• Stephan Kudelka · Radeberg, DE
• Uwe Schroeder · Fishkill, US
• Brian Lee · New York, US

Key dates

• Filing date: Jun 19, 2000
• Grant date: Jan 1, 2002
• Expiry date: Jun 19, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/053

Abstract

A method of forming a vertically-oriented device in an integrated circuit using a selective wet etch to remove only a part of the sidewalls in a deep trench, and the device formed therefrom. While a portion of the trench perimeter (e.g., isolation collar 304) is protected by a mask (e.g., polysilicon 318), the exposed portion is selectively wet etched to remove selected crystal planes from the exposed portion of the trench, leaving a flat substrate sidewall (324) with a single crystal plane. A single side vertical trench transistor may be formed on the flat sidewall. A vertical gate oxide (e.g. silicon dioxide 330) of the transistor formed on the single crystal plane is substantially uniform across the transistor channel, providing reduced chance of leakage and consistent threshold voltages from device to device. In addition, trench widening is substantially reduced, increasing the device to device isolation distance in a single sided buried strap junction device layout.