Self modifying code to test all possible addressing modes
US6336212B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 15, 2000 |
| Grant date | Jan 1, 2002 |
| Priority date | — |
| Expiry date | Sep 30, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for testing a plurality of addressing modes in a microprocessor comprising executing a test instruction which is stored in memory, subsequently overwriting the test instruction in memory and then re-executing the test instruction. The test instruction is stored at a memory location which is within a code segment. A data segment is defined to overlap with the code segment and a portion of the test instruction is overwritten by storing data within the overlapping data segment. The overwritten portion of the test instruction identifies the addressing mode of the test instruction and the stored data represents the next addressing mode to be tested. In an x86 architecture, the overwritten portion of the test instruction may comprise a MODR/M byte and an SIB byte, each of which may take on values from 00 to ff (hexadecimal). The addressing modes of the microprocessor may therefore be tested by sequentially incrementing the MODR/M and SIB bytes and executing the test instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.