Process of forming a capacitor with multi-level interconnection technology
US6336262B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 1997 |
| Grant date | Jan 8, 2002 |
| Priority date | — |
| Expiry date | Apr 30, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49213
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A capacitor having a multilevel interconnection technology and process thereof. Also disclosed is a process of electrically connecting a capacitor to an object, comprising the steps of first obtaining a capacitor. At least one solder ball is reflowed and secured onto the capacitor. The solder ball is in electrical communication with the capacitor through a contacting means. On this reflowed solder ball a cap of low melting point metal is secured. This can be done in a number of ways. The preferred way is to positioning a mask over the solder ball such that a portion of the solder ball is exposed through openings in the mask. At least one layer of a low melting point metal is deposited on the exposed surface of the solder ball through the mask, and thereby forming a capacitor with a multilevel interconnect cap. The low melting point metal can interact with the surface of the solder ball to form a cap of an eutectic or a liquefied portion. The cap portion can then be joined to the object.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.