Method for ramped current density plating of semiconductor vias and trenches
US6340633B1 · kind B1 · utility
16Cited by
42References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 26, 1999 |
| Grant date | Jan 22, 2002 |
| Priority date | — |
| Expiry date | Mar 26, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is provided for forming conductive layers in semiconductor channels and vias by using ramped current densities for the electroplating process. The lower density currents are used initially to deposit a fine grain conductive layer in the vias and then higher densities are used to deposit a large grain conductive layer in the channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.