Semiconductor device having a gate electrode with enhanced electrical characteristics
US6344397B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 5, 2000 |
| Grant date | Feb 5, 2002 |
| Priority date | — |
| Expiry date | Jan 5, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/518
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In one illustrative embodiment, the present invention is directed to forming a masking layer (104) above a semiconducting substrate (102), forming an opening (105) in the masking layer (104), forming sidewall spacers (109) that define an exposed surface of said substrate lying between the sidewall spacers (109), and forming a layer of gate dielectric material (108) on the exposed surface of the substrate. The method further comprises forming a layer of polysilicon in the opening (105) and on the gate dielectric layer (108), removing portions of the polysilicon layer lying outside the opening (105) to define a gate electrode (111), forming a layer of refractory metal above the gate electrode (111), converting at least some of the refractory metal layer to a metal silicide region (112) above the gate electrode (111), and removing the masking layer (104).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.