Flash memory permitting simultaneous read/write and erase operations in a single memory array
US6345000B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 25, 1998 |
| Grant date | Feb 5, 2002 |
| Priority date | — |
| Expiry date | Nov 25, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile Flash memory simultaneously performs an erase operation and a write or read operation in the same array of memory cells. The memory has a row based sector architecture, i.e., sectors that contain one or more complete rows of memory cells. During an erase operation, an erase voltage applied to the source lines for one or more rows corresponding to a sector does not affect write or read operations being performed in other sectors, i.e., other rows. Similarly, voltages applied to row lines for access to a memory cell have no effect on the erase operation being performed in another sector. A column line voltage applied for access to a memory cell has little affect on the erase operation. The memory can implement a look-ahead erase for a continuous reading or writing operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.