Memory circuit with local isolation and pre-charge circuits
US6345006B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 21, 2000 |
| Grant date | Feb 5, 2002 |
| Priority date | — |
| Expiry date | Aug 21, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4091
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A sense amplifier circuit that decreases the write cycle row to column time and pre-charge time by locally isolating the digit lines from the N-sense and P-sense amplifier circuits and pre-charging the isolated digit lines is disclosed. A local isolation device is provided between the N-sense amplifier and the digit lines of a memory array. Similarly, a local isolation device is provided between the P-sense amplifier and the digit lines of the memory array. The local isolation devices are controlled by the inversion phase of the column select signal. Additionally, a local pre-charge circuit is provided to pre-charge the isolated digit lines to a voltage potential, such as for example Vcc. The local isolation and pre-charging of the digit lines provides for a faster write cycle, faster pre-charge time and faster row to column time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.