Method of improving alignment for semiconductor fabrication
US6346456B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 9, 1998 |
| Grant date | Feb 12, 2002 |
| Priority date | — |
| Expiry date | Nov 9, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of improving alignment for semiconductor fabrication. A semiconductor substrate is provided. The semiconductor comprises a field region and a scribe line on which an alignment mark is comprised. A plurality of shallow trench isolation structures are formed on the field region and the alignment mark. Each of the shallow trench isolation structures is filled with an insulation layer. The insulation layer within shallow trench isolation trench on the alignment is partly or completely removed. A gate oxide layer and a poly-silicon layer are formed over the semiconductor substrate in sequence. The poly-silicon layer is defined to form a poly-line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.