Linear address extension and mapping to physical memory using 4 and 8 byte page table entries in a 32-bit microprocessor
US6349380B1 · kind B1 · utility
75Cited by
12References
18Claims
0Family size
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Key dates
| Filing date | Mar 12, 1999 |
| Grant date | Feb 19, 2002 |
| Priority date | — |
| Expiry date | Mar 12, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0292
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor for providing an extended linear address of more than 32 bits. The extended linear address may be provided by concatenating a linear address with a segment selector extension, or by concatenating the values from two registers. Hierarchical translation of a linear address to a physical address is performed in which the number of levels in the hierarchy depends upon whether the linear address is an extended linear address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.