Low-K sub spacer pocket formation for gate capacitance reduction
US6351013B1 · kind B1 · utility
231Cited by
10References
6Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 13, 1999 |
| Grant date | Feb 26, 2002 |
| Priority date | — |
| Expiry date | Jul 13, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/90
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The capacitance between the gate electrode and the source/drain regions of a semiconductor device is reduced by forming sub-spacers of a low dielectric constant (K) material at the corners of the gate electrode above the source/drain regions. Subsequently, insulating sidewall spacers are formed over the sub-spacers to shield-shallow source/drain regions from subsequent impurity implantations. The resulting semiconductor device exhibits reduced capacitance between the gate electrode and the source/drain regions, while maintaining circuit reliability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.