Vertically stacked field programmable nonvolatile memory and method of fabrication
US6351406B1 · kind B1 · utility
355Cited by
58References
26Claims
0Family size
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Key dates
| Filing date | Nov 15, 2000 |
| Grant date | Feb 26, 2002 |
| Priority date | — |
| Expiry date | Nov 15, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/76
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.