Patent · US Expired

Memory cell configuration

US6351408B1 · kind B1 · utility

32Cited by

4References

9Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Siegfried Schwarzl · Neubiberg, DE
Lothar Risch · Neubiberg, DE

Key dates

Filing date	Apr 6, 2000
Grant date	Feb 26, 2002
Priority date	—
Expiry date	Apr 6, 2020

Classification

Technology area (CPC H)Electricity
CPC primaryH10B61/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A memory cell configuration has word lines and bit lines running transversely with respect thereto. Memory elements with a magnetoresistive effect are respectively connected between one of the word lines and one of the bit lines. The memory elements are disposed in at least two layers one above the other.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.