Vertically configured chamber used for multiple processes
US6352623B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 1999 |
| Grant date | Mar 5, 2002 |
| Priority date | — |
| Expiry date | Dec 17, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S134/902
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
The present invention relates to a containment chamber that is used for carrying out multiple processing steps such as depositing on, polishing, etching, modifying, rinsing, cleaning, and drying a surface on the workpiece. In one example of the present invention, the chamber is used to electro chemically mechanically deposit a conductive material on a semiconductor wafer. The same containment chamber can then be used to rinse and clean the same wafer. As a result, the present invention eliminates the need for separate processing stations for depositing the conductive material and cleaning the wafer. Thus, with the present invention, costs and physical space are reduced while providing an efficient apparatus and method for carrying out multiple processes on the wafer surface using a containment chamber.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.