Optimized decoupling capacitor using lithographic dummy filler

US6353248B1 · kind B1 · utility

Assignees

• Infineon Technologies AG · DE
• International Business Machines Corporation · US

Inventors

• Armin Reith · Wappingers Falls, US
• Louis L. Hsu · Fishkill, US
• Henning Haffner · Pawling, US
• Gunther Lehmann · Poughkeepsie, US

Key dates

• Filing date: Apr 28, 2000
• Grant date: Mar 5, 2002
• Expiry date: Apr 28, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/50

Abstract

A method to optimize the size and filling of decoupling capacitors for very large scale integrated circuits (VLSI) using existing lithographic fillers. The method combines the automatic or manual generation of lithographic fill patterns with the forming of the capacitors. According to the method, when the chip layout is about to be finished, all remaining empty space on the chip gets identified by a layout tool. Then, the closest power-supply nets get extracted. All power supplies and their combinations are sorted in a connection table which determines the appropriate types of capacitances once the power-supply nets closest to the empty spaces extracted from the layout. The empty spaces are then assigned appropriate decoupling capacitances. Decoupling capacitors generated by the method are suitable for VLSI power supplies for noise reduction.