PLD with on-chip memory having a shadow register
US6353552B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 26, 2001 |
| Grant date | Mar 5, 2002 |
| Priority date | — |
| Expiry date | Mar 26, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/177
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus for initializing and determining the contents of a memory block in a programmable logic device. One apparatus includes a logic element, programmably configurable to implement user-defined combinatorial or registered logic functions, and a memory block to store data. The memory block is coupled to the logic element. The memory block includes a memory storage cell to store a first data bit, a shadow cell to store a second data bit, and a transfer circuit. When a first control line of a transfer circuit is asserted, the second bit is transferred from the shadow cell to the memory storage cell. When a second control line of the transfer circuit is asserted, the first bit is transferred from the memory storage cell to the shadow cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.