Subtractive oxidation method of fabricating a short-length and vertically-oriented channel, dual-gate, CMOS FET
US6355532B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 6, 1999 |
| Grant date | Mar 12, 2002 |
| Priority date | — |
| Expiry date | Oct 6, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/43
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A short vertical channel, dual-gate, CMOS FET is fabricated by forming a plurality of channel segments in a starting material that extend longitudinally between source and drain areas. The channel segments are laterally separated from one another by spaces and are preferably formed from pillars of starting material located between the spaces. The pillars are laterally oxidized and the oxidation is removed to reduce the width of the pillars and form the channel segments. A gate structure is formed in the spaces between the channel segments. The width of each pillar is defined by conventional, contemporaneous photolithographic exposure and etching, but the width of each channel segment is substantially less than the width of the etch resistant barrier created photolithographically. The relatively narrow channel widths allow fully-depleted and fully-inverted conductivity characteristics which enhance the conductivity characteristics of the FET despite its reduced size, without silicon on insulator (SOI) constructions or epitaxial substrates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.