On chip data comparator with variable data and compare result compression
US6357027B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | May 17, 1999 |
| Grant date | Mar 12, 2002 |
| Priority date | — |
| Expiry date | May 17, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory chip, in accordance with the present invention, includes a memory array including memory components to be tested. A pattern generator provides reference data to be input to and stored in the memory array. A comparator is formed on the memory chip for comparing the reference data from the pattern generator and the stored data from the memory array. The comparator further includes logic circuitry for comparing the reference data to the stored data from the memory array to provide a compare result having a matched state if the stored data matches the reference data and otherwise an unmatched state. A plurality of latches are included for receiving the compare result from the logic circuitry, the latches having a first state associated with the matched state wherein the first state is altered to a second state if the unmatched state is received from the logic circuitry. A register for storing and outputting the first and second states of the latches to provide a test result is also included.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.