Gerd Frankowsky
47Patents
9h-index
27Co-inventors
67Inventor score
Filing activity: Feb 25, 1999 → Aug 31, 2006
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6845554B2 | Method for connection of circuit units | Emerging Cross-Sectional Technologies | 96 | Expired |
| US6714418B2 | Method for producing an electronic component having a plurality of chips that are stacked one above the other and contact-connected to one another | Electricity | 55 | Expired |
| US6483764B2 | Dynamic DRAM refresh rate adjustment based on cell leakage monitoring | Physics | 50 | Expired |
| US6603694B1 | Dynamic memory refresh circuitry | Physics | 50 | Expired |
| US7074696B1 | Semiconductor circuit module and method for fabricating semiconductor circuit modules | Electricity | 30 | Expired |
| US6357027B1 | On chip data comparator with variable data and compare result compression | Physics | 18 | Expired |
| US6426911B1 | Area efficient method for programming electrical fuses | Physics | 13 | Expired |
| US6909642B2 | Self trimming voltage generator | Physics | 12 | Expired |
| US6601205B1 | Method to descramble the data mapping in memory circuits | Physics | 9 | Expired |
| US6730989B1 | Semiconductor package and method | Electricity | 8 | Expired |
| US6853233B1 | Level-shifting circuitry having “high” output impedance during disable mode | Electricity | 8 | Expired |
| US6570794B1 | Twisted bit-line compensation for DRAM having redundancy | Physics | 7 | Expired |
| US6937531B2 | Memory device and method of storing fail addresses of a memory cell | Physics | 7 | Expired |
| US7208968B2 | Test system for testing integrated chips and an adapter element for a test system | Physics | 5 | Expired |
| US6657453B2 | Semiconductor wafer testing system and method | Physics | 5 | Expired |
| US6367027B1 | Skew pointer generation | Physics | 5 | Expired |
| US6727586B2 | Semiconductor component | Electricity | 5 | Expired |
| US6677770B2 | Programmable test socket | Physics | 5 | Expired |
| US7061260B2 | Calibration device for the calibration of a tester channel of a tester device and a test system | Physics | 4 | Expired |
| US6608783B2 | Twisted bit-line compensation | Physics | 4 | Expired |
| US7034559B2 | Integrated test circuit in an integrated circuit | Physics | 4 | Expired |
| US6734474B2 | Integrated semiconductor circuit having contact points and configuration having at least two such circuits | Electricity | 4 | Expired |
| US7437627B2 | Method and test device for determining a repair solution for a memory module | Physics | 3 | Expired |
| US6809972B2 | Circuit technique for column redundancy fuse latches | Physics | 3 | Expired |
| US6961880B2 | Recording test information to identify memory cell errors | Physics | 3 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.