Vertical PNP bipolar transistor and its method of fabrication
US6359317B1 · kind B1 · utility
14Cited by
2References
6Claims
0Family size
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Key dates
| Filing date | Dec 28, 1998 |
| Grant date | Mar 19, 2002 |
| Priority date | — |
| Expiry date | Dec 28, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/401
Abstract
A bipolar vertical PNP transistor compatible with CMOS processing and useful in a complementary BiMOS structure is characterized in that it is devoid of an epitaxial layer and employs a high-energy implanted phosphorus layer to provide N-type substrate isolation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.