System and method of compensating for non-linear voltage-to-delay characteristics in a voltage controlled delay line
US6359487B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 3, 2000 |
| Grant date | Mar 19, 2002 |
| Priority date | — |
| Expiry date | Apr 3, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S331/02
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system and method of compensating for non-linear voltage-to-delay characteristics in a voltage controlled delay line such as those used in delay-locked loop (“DLL”) circuits in integrated circuit (“IC”) devices such as double data rate (“DDR”) dynamic random access memory (“DRAM”), static random access memory (“SRAM”), processors and other IC devices. The technique renders the incremental changes for each correction to the control voltages to the voltage controlled delay line a function of the control voltage itself. The change in the control voltage becomes smaller as the control voltage gets lower thereby effectively precluding over-correction and excessive jitter. Since the smallest corrections to be made will occur when the control voltage is much lower than its initial value, the majority of the corrections made in moving from the initialization point to the final lock point in the DLL loop will be much larger than the final corrections thereby resulting in only minimally slower locking times than would otherwise be the case. The changes in delay become inherently smaller if the lock point is at a higher VR value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.