Data cache having store queue bypass for out-of-order instruction execution and method for same
US6360314B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 14, 1998 |
| Grant date | Mar 19, 2002 |
| Priority date | — |
| Expiry date | Jul 14, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3826
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bypass mechanism is disclosed for a computer system that executes load and store instructions out of order. The bypass mechanism compares the address of each issuing load instruction with a set of recent store instructions that have not yet updated memory. A match of the recent stores provides the load data instead of having to retrieve the data from memory. A store queue holds the recently issued stores. Each store queue entry and the issuing load includes a data size indicator. Subsequent to a data bypass, the data size indicator of the issuing load is compared against the data size indicator of the matching store queue entry. A trap is signaled when the data size indicator of the issuing load differs from the data size indicator of the matching store queue entry. The trap signal indicates that the data provided by the bypass mechanism was insufficient to satisfy the requirements of the load instruction. The bypass mechanism also operates in cases in which multiple prior stores to the same address are pending when a load that needs to read that address issues.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.