CVD/PVD/CVD/PVD fill process
US6361880B1 · kind B1 · utility
2Cited by
9References
5Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Dec 22, 1999 |
| Grant date | Mar 26, 2002 |
| Priority date | — |
| Expiry date | Dec 22, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/2495
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is provided in which intermediate sized structures can be filled without forming voids during the fill process. The methods involve use of a sequence of CVD/PVD/CVD/PVD steps. The methods are especially effective for filling “intermediate” size features in damascene and dual damascene structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.