Method for forming a semiconductor device with an opening in a dielectric layer

US6362071B1 · kind B1 · utility

Assignee

• Motorola, Inc. · US

Inventors

• Bich-Yen Nguyen · Austin, US
• William J. Taylor, Jr. · Clifton Park, US
• Philip J. Tobin · Austin, US
• David L. O'Meara · Albany, US
• Percy V. Gilbert · Austin, US
• Yeong-Jyh T. Lii · Austin, US
• Victor Wang · Orange, US

Key dates

• Filing date: Apr 5, 2000
• Grant date: Mar 26, 2002
• Expiry date: Apr 5, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

In accordance with one embodiment of the present invention, a method is disclosed for forming a semiconductor device having an isolation region (601). A dielectric layer (108) is deposited and etched to form isolation regions (102, 605) having top portions that are narrower than their bottom portions, thereby a tapered isolation region is formed. Active regions (601, 603) are formed using an epitaxial process in the regions between the isolation regions. The resulting active regions (601, 603) have a greater amount of surface area near a top portion, than near a bottom portion. Transistors (721, 723) having opposite polarities are formed within the active areas.