Collimated sputtering of semiconductor and other films
US6362097B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 14, 1998 |
| Grant date | Mar 26, 2002 |
| Priority date | — |
| Expiry date | Jul 14, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0321
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Thin semiconductor films or layers having a pre-selected degree of crystallinity, from amorphous material to poly-crystalline material, can be obtained by selecting an appropriate aspect ratio for a collimator used during a sputtering process. The orientation of the deposited film also can be tailored by selection of the collimator aspect ratio. Sputtered collimation permits highly crystalline films to be formed at temperatures significantly below the annealing temperature of the sputtered material. Thus, required fabrication steps and increase the throughput of the use of low temperatures allows films of substantially greater crystallinity and carrier mobility to be fabricated on glass and other low temperature substrates. Additionally, thin semiconductor Trapped charge defects also can be reduced by grounding the collimator to provide electrical isolation between the charged plasma particles and the substrate on which the sputtered layer is to be formed. Dielectric films having a thickness as small as several hundred å can be formed to fabricate high transconductance devices with high breakdown strengths. improved electrically active interfaces, such as a rectifying junctio…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.