Low column leakage NOR flash array-single cell implementation
US6363014B1 · kind B1 · utility
22Cited by
7References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 23, 2000 |
| Grant date | Mar 26, 2002 |
| Priority date | — |
| Expiry date | Oct 23, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a NOR-type flash memory array architecture, comprising a plurality of flash memory cells spatially organized in a column, wherein a drain terminal of each of the flash memory cells are coupled together and form an array bitline input. Further, a control gate terminal of each of the flash memory cells is coupled to a different wordline input and at least one of the flash memory cells has a source terminal which is electrically isolated from one or more of the source terminals of the other flash memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.