Mechanism for handling 16-bit addressing in a processor
US6363471B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 3, 2000 |
| Grant date | Mar 26, 2002 |
| Priority date | — |
| Expiry date | Jan 3, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1036
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes an address generation unit (AGU) which adds address operands and the segment base. The AGU may add the segment base and the displacement while other address operands are being read from the register file. The sum of the segment base and the displacement may subsequently be added to the remaining address operands. The AGU receives the addressing mode of the instruction, and if the addressing mode is 16 bit, the AGU zeros the carry from the sixteenth bit to the seventeenth bit of the sums generated therein. Additionally, in parallel, the AGU determines if a carry from the sixteenth bit to the seventeenth bit would occur if the logical address were added to the segment base. In one embodiment, the sum of the address operands and the segment base, with carries from the sixteenth bit to the seventeenth bit zeroed, and the carry generated in parallel are provided to a translation lookaside buffer (TLB), which stores translations in the same format (sum and carry). In another embodiment, the AGU corrects the most significant bits of the generated sum based on the carry. The AGU and/or TLB may provide reduced address generation latency while handling the 16 bit address…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.