Method for testability analysis and test point insertion at the RT-level of a hardware development language (HDL) specification
US6363520B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 16, 1998 |
| Grant date | Mar 26, 2002 |
| Priority date | — |
| Expiry date | Jun 16, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318364
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method is provided for producing a synthesizable RT-Level specification, having a testability enhancement from a starting RT-Level specification representative of a circuit to be designed, for input to a synthesis tool to generate a gate-level circuit. The method includes the steps of performing a testability analysis on a Directed Acyclic Graph by computing and propagating Testability Measures forward and backward through VHDL statements, identifying the bits of each signal and/or variable, and adding test point statements into the specification at the RT-Level to improve testability of the circuit to be designed. The computation of Controllability and Observability method is purely functional, and does not subsume the knowledge of a gate-level implementation of the circuit being analyzed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.