Self-aligned double-gate MOSFET by selective epitaxy and silicon wafer bonding techniques
US6365465B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 19, 1999 |
| Grant date | Apr 2, 2002 |
| Priority date | — |
| Expiry date | Mar 19, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76275
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A structure and a method of manufacturing a double-gate metal oxide semiconductor transistor includes forming a laminated structure having a single crystal silicon channel layer and insulating oxide and nitride layers on each side of the single crystal silicon channel, forming openings in the laminated structure, forming drain and source regions in the openings, doping the drain and source regions, forming a mask over the laminated structure, removing portions of the laminated structure not protected by the mask, removing the mask and the insulating oxide and nitride layers to leave the single crystal silicon channel layer suspended from the drain and source regions, forming an oxide layer to cover the drain and source regions and the channel layer, and forming a double-gate conductor over the oxide layer such that the double-gate conductor includes a first conductor on a first side of the single crystal silicon channel layer and a second conductor on a second side of the single crystal silicon channel layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.