Method of fabricating an integrated circuit

US6365474B1 · kind B1 · utility

Assignee

• Motorola, Inc. · US

Inventors

• Jeffrey M. Finder · Chandler, US
• Kurt Eisenbeiser · Tempe, US
• Bich-Yen Nguyen · Austin, US

Key dates

• Filing date: Jun 22, 2000
• Grant date: Apr 2, 2002
• Expiry date: Jul 12, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/017

Abstract

A transistor (12) and method of making an integrated circuit (10) uses a chromium based sacrificial gate (22A) to align, dope and activate source and drain portions (36, 38, 52, 53,) of the transistor. The transistor is subjected to a high temperature to activate the source and drain, which would damage a high permittivity gate dielectric. The sacrificial gate is removed by etching with ceric ammonia nitrate. A high permittivity gate dielectric (72) and a final gate electrode (74) are formed over a channel (30) of the transistor. Electrodes (76, 78) are formed for coupling to the source and drain.