Semiconductor configuration and corresponding production process

US6368970B1 · kind B1 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Ayad Abdul-Hak · Dresden, DE
• Achim Gratz · Dresden, DE
• Christoph Ludwig · Radeberg, DE
• Reinhold Rennekamp · Dresden, DE
• Elard Stein Von Kamienski · Dresden, DE
• Peter Wawer · Dresden, DE

Key dates

• Filing date: Aug 24, 2000
• Grant date: Apr 9, 2002
• Expiry date: Aug 24, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A process for producing a semiconductor configuration includes the steps of providing a semiconductor substrate, providing a buffer oxide layer on the semiconductor substrate and providing a hard mask on the buffer oxide layer. An STI trench is etched by using the hard mask and a liner oxide layer is provided in the STI trench. The hard mask is removed to expose the buffer oxide layer and the buffer oxide layer is removed by an etching process. The buffer oxide layer is etched more rapidly than the liner oxide layer in the etching process. A gate oxide layer is provided on the semiconductor substrate. A semiconductor configuration is also provided.