Dual track/stepper interface configuration for wafer processing
US6368985B1 · kind B1 · utility
2Cited by
7References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 30, 2000 |
| Grant date | Apr 9, 2002 |
| Priority date | — |
| Expiry date | May 30, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F7/70991
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An apparatus for processing semiconductor wafers includes a single imaging stepper for exposing wafers processed on a first track and a second track. A method for processing semiconductor wafers includes selecting one of a first coater and a second coater for coating a first wafer with a photoresist. The coated wafer is exposed in a single stepper to form an exposed wafer. An operator selects one of a first developer and second developer to develop the exposed wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.